ICSJ 2010 Technical Program
(Aug. 24-26, 2010)

August 24, 2010

Room 213: Session Chair: Hirofumi Nakajima
 9:30 - 9:40 Opening Remarks:
   Hirofumi Nakajima (Executive Chair, IEEE CPMT Symposium Japan; Renesas Electronics Corporation)
 9:40 - 9:50 Welcome Talk CPMT President:
   Rolf Aschenbrenner (President, CPMT Society, IEEE; Fraunhofer IZM)
 9:50 - 10:35 Plenary Speech 1
  Materials - Crucial Enabler for Packaging Innovation,
    William Chen (Senior Technical Advisor ASE Group, IEEE/CPMT Society Distinguished Lecturer)
10:45 - 11:30 Plenary Speech 2
  Difficult Challenges and potential solutions for Advanced Packaging,
    W. R. Bottoms (Chair, A&P TWG, ITRS; Chairman, Third Millennium Test Solutions)
11:30 - 12:10 Plenary Speech 3
  Recent Advances on Nano-materials for Advanced Packaging Applications,
    C. P. Wong (Dean of the Faculty of Engineering, The Chinese University of Hong Kong)

Room 213
13:00 - 14:40 Session 1: Advanced Package (AP-1)
Session Chair: Shoji Uegaki, Klaus Pressel

1-1

Module Miniaturization by ultra thin Package Stacking
Thomas Loher1, David Schutze2, Andreas Ostmann2 and Rolf Aschenbrenner2 / Tecknische Universitat Berlin1, Fraunhofer IZM2

1-2

Development of Super Thin TSV PoP
Flynn Carson1, Kazuo Ishibashi2, Seung Wook Yoon3, Pandi Chelvam Marimuthu3 and Dzafir Shariff3 / STATS ChipPAC, Inc.1, Nokia Japan Co., Ltd.2, STATS ChipPAC Singapore, Ltd.3

1-3

A wafer-level system integration technology for flexible pseudo-SOC incorporates MEMS-CMOS heterogeneous devices
Hiroshi Yamada1, Yutaka Onozuka1, Atsuko Iida1, Kazuhiko Itaya1, Hideyuki Funaki1, Kazuhiro Takahashi2 and Hiroshi Toshiyoshi2/ Toshiba Corporation1, The University of Tokyo2


Author's Interview (20 min.)

15:10 - 16:50 Session 2: Advanced Package (AP-2)
Session Chair: Shigenori Aoki, C.P. Hung

2-1

Alternative Process and Support Material for Embedded Fine-pad-pitch LSI Package
Hideya Murai, Kentaro Mori, Masaya Kawano and Shintaro Yamamichi /Renesas Electronics Corporation

2-2

Preparation of ferroelectric capacitor films onto the releasable substrate and its application to nano-transfer method
Masaaki Ichiki1.3,4 , Keita Iimura1, Toshifumi Hosono1, Keisuke Kuroki1, Fumiaki Tomioka1, Tadatomo Suga1,3 Ryutaro Maeda2 and Toshihiro Itoh2, 3 /The University of Tokyo1, National Institute of Advanced industrial Science and Technology(AIST)2, JST-CREST3, JST-PRESTO4

2-3

Embedded Wafer Level Ball Grid Array (eWLB) Technology for System Integration
Klaus Pressel, Gottfried Beer, Thorsten Meyer, Maciej Wojniwski, Markus Fink, Gerals Ofner and Bernd Romer / Infineon Technologies AG.

2-4

High Density Substrate Solution for Complex High Pin Count Flip-Chip Applications
Vern Solberg1 and Vage Oganesian2 / STC-Madison1,Tessera2


Author's Interview (20 min.)

Room 212
13:00 - 14:40 Session 3: Board Level Reliability (BR-1)
Session Chair: Michitaka Kimura, Jie Xue

3-1

Invited : Mechanical and Material Reliability in Board Level Solder Joints
Masazumi Amagai / Texas Instruments Japan Ltd.

3-2

Effect of Mild Aging on Package Drop Performance for Lead Free Solders
SeokHo Na, SeWoong Cha, WonJoon Kang, TaeSeong Kim, TaeKyung Hwang and JinYoung Khim / Amkor Technology Korea

3-3

Next Generation Substrate for High Density and Thin Package
Toru Furuta / IBIDEN CO.,LTD.

3-4

PoP Prototyping by determination of matter transport effects
Lutz Meinshausen1 , Kirsten Weide-Zaage1, Wei Feng2 and Helene Fremont2 / Leibniz University Hannover1, Universite Bordeaux I2


Author's Interview (20 min.)

15:10 - 16:50 Session 4: Board Level Reliability (BR-2)
Session Chair: Michitaka Kimura, Jie Xue

4-1

Modeling of Board Level Solder Joint Reliability under Mechanical Drop Test with the Consideration of Plastic Strain Hardening of Lead-free Solder
Z. J. Xu, T. Jiang, F. B. Song, Jeffery C. C. Lo and S. W. Ricky Lee / Hong Kong University of Science and Technology

4-2

Effect of Solders, Underfills and Substrates on Reliability of Flip-Chip Bonding of Low-k Semiconductor Chips
Kenji Terada, Takayuki Nejime, Takafumi Ooyoshi, Kaoru Kobayashi and Kimihiro Yamanaka / KYOCERA SLC Technologies Corporation

4-3

Health monitoring method for load assessment in reliability design of printed circuit board
Kenji Hirohata, Katsumi Hisano, Yosuke Hisakuni, Takahiro Omori and Minoru Mukai / Toshiba Corporation

4-4

Effects of the crystallographic orientation of Sn grain during electromigration test
Kiju Lee1, Keun-Soo Kim1, Kimihiro Yamanaka2, Yutaka Tsukada1, Soichi Kuritani3, Mimoru Ueshima4 and Katsuaki Suganuma1 / Osaka University1, KYOCERA SLC Technologies Corporation2, ESPEC.CORP3, SENJU METAL INDUSTRY CO.,LTD4


Author's Interview (20 min.
)

Room 211
13:00 - 14:40 Session 5: Electrical Design (ED-1)
Session Chair: Toshio Sudo, Yutaka Uematsu

5-1

Design Trade-Off for Resonance Reduction of Multiple Power Planes in Super Ball Grid Array (SBGA) Package
GaWon Kim1, SeungJae Lee1, JiHeon Yu1, Ozgur Misman2, KiCheol Bae1, TaeKi Kim1, Sangwoong Lee1 and JinYoung Kim1 / Amkor Technology Korea1, Amkor Technology Inc.2

5-2

Fast Power Integrity Estimation Method by Use of LSI Power-pn Model
Takashi Harada, Masashi Ogawa and Manabu Kusumoto / NEC Corporation

5-3

Modeling and Analysis of Differential Signal Through Silicon Via (TSV) in 3D IC
Joohee Kim1, Jun So Pak1, Jonghyun Cho1, Junho Lee2, Hyungdong Lee2, Kunwoo Park2 and Joungho Kim1/ Korea Advanced Institute of Science and Technology (KAIST)1, Hynix Semiconductor Inc.2

5-4

A Stopband Enhanced EBG Power/ground Plane based on Via Location Design
Chuen-De Wang and Tzong-Lin Wu / National Taiwan University


Author's Interview (20 min.
)

15:10 - 16:25 Session 6: Electrical Design (ED-2)
Session Chair: Takashi Harada, Hideki Osaka

6-1

TSV Mutual Inductance Effect on Impedance of 3D Stacked On-Chip PDN with Multi-TSV Connections
Jun So Pak1, Jonghyun Cho1, Joohee Kim1, Junho Lee2, Hyungdong Lee2, Kunwoo Park2 and Joungho Kim1 /Korea Advanced Institute of Science and Technology (KAIST) 1, Hynix Semiconductor Inc.2

6-2

Through Co-Design to Optimize Power Delivery Distribution System Using Embedded Discrete De-coupling Capacitor
Chen-Chao Wang1, Hung-Hsiang Cheng1, Chi-Tsung Chiu1, Chih-Pin Hung1, Chih-Wen Kuo2 and Toshihide Kitazawa3 / Advanced Semiconductor Engineering Inc1, National Sun Yat-Sen University2, Ritsumeikan University3

6-3

Impulse responses of on-chip power supply networks with varying conditions
Yutaka Uematsu, Hideki Osaka, Masayoshi Yagyu and Tatsuya Saito / Hitachi Ltd.


- Author's Interview (20 min.)
-

August 25, 2010

Room 213:  Session Chair: Ricky Lee
 9:30 - 10:30 Plenary Speech 4
  Recent Progress in Surface Activated Bonding Method,
    Tadatomo Suga (General Chair, IEEE CPMT Symposium Japan; School of Engineering of The University of Tokyo)
 10:30 - 11:15 Plenary Speech 5
  3D System-in-Package Technologies for Multifunctional Systems,
    Klaus-Dieter Lang (Fraunhofer IZM)

 11:15 - 12:00 Plenary Speech 6
  3D System Integration - Opportunities and challenges in the supply chain,
    Eric Beyne (Interuniversity Microelectronics Center)


Room 212

13:00 - 14:40 Session 7: Interconnect (IC)
Session Chair: Hirofumi Nakajima, Kuo-Ning Chiang

7-1

Wire Bonding with Pd-Coated Copper Wire
Horst Clauberg1, Bob Chylak1, Nelson Wong1, Johnny Yeung2, Eugen Milke3 / Kulicke & Soffa Ind, Inc.1, Heraeus Materials Singapore Pte Ltd.2, WC Heraeus GmbH3

7-2

Fine Pitch Cu Wire Bonding - As Good As Gold
Bernd K. Appelt, William T. Chen, Andy Tseng, and Yi‐Shao Lai / ASE Group Inc.

7-3

Study of EMC for Cu bonding wire application
Hidetoshi Seki1, Chen Ping2, Hiroshi Nakatake3, Shin-ichi Zenbutsu1 and Shingo Itoh1 / SUMITOMO BAKELITE Co., Ltd.1, SUMITOMO BAKELITE SINGAPORE PTE. Ltd.2, S.B. RESEARCH Co., Ltd.3

7-4

Process Design of Self-Replication for Micro Bump Formation
Kiyokazu Yasuda / Nagoya University


- Author's Interview (20 min.)
-

15:10 - 16:50 Session 8: Optical vs. Electrical Transmission (OE-1)
Session Chair: Kanji Otsuka, Toshio Sudo

8-1

Invited : Potential of Wavelength-Division-Multiplexing Optical-Interconnects for Next-Generation System in Packaging
Shogo Ura1 and Kenji Kintaka2 / Kyoto Institute of Technology1, Association of Super-Advanced Electronics Technology (ASET)2

8-2

Study on Novel Concept of Transmission Signal Assisted with Evanescent Wave Energy
Kaoru Hashimoto, Kazuo Kohno, Yutaka Akiyama, Hisashi Kikuchi and Kanji Otsuka / Meisei University

8-3

A Feasibility Study of Proximity Interconnect Technology Utilizing Transmission Line Coupling
Daisuke Iguchi1, Yutaka Akiyama2, Fumiaki Fujii2 and Kanji Otsuka2 /Fuji Xerox Co., Ltd.1, Meisei University2

8-4

Analysis of On-Board Antenna Modules for the Millimeter-Wave Intra-Connect system
Sho Ohashi, Takahiro Takeda, Hirofumi Kawamura, Yasuhiro Okada, Masahiro Uno, Yoshiyuki Akiyama and Kenichi Kawasaki / Sony Corporation


Author's Interview (20 min.)

Room 213
13:00 - 14:40 Session 9: 3D Integration (3D-1)
Session Chair: Hiroshi Yamada, Rolf Aschenbrenner

9-1

Development of high accuracy wafer thinning and pickup technology for thin wafer(die)
Chuichi Miyazaki1,2, Haruo Shimamoto1,2, Toshihide Uematsu1,2, Yoshiyuki Abe1,2, Kosuke Kitaichi1,2, Tadahiro Morifuji1,3 and Shoji Yasunaga1,3 / Association of Super-Advanced Electronics Technology (ASET) 1, Renesas Technology Corp2., ROHM Co., Ltd. 3

9-2

Development of High speed Copper CMP Slurry for TSV application based on Friction analysis
Jin Amanokura1, Hiroshi Ono1 and Kyoko Hombo2 / Hitachi Chemical Co., Ltd.1, Hitachi Ltd.2

9-3

Evaluation of Surface Microroughness for Surface Activated Bonding
Kei Tsukamoto, Eiji Higurashi and Tadatomo Suga / The University of Tokyo

9-4

Guard-Ring Effect for Through Silicon Via (TSV) Noise Coupling Reduction
Jonghyun Cho1, Kihyun Yoon1, Jun So Pak1, Joohee Kim1, Junho Lee2, Hyungdong Lee2, Kunwoo Park2 and Joungho Kim1 /Korea Advanced Institute of Science and Technology (KAIST)1, Hynix Semiconductor Inc.2


Author's Interview (20 min.)

15:10 - 16:50 Session 10: 3D Integration (3D-2)
Session Chair: Masahiro Aoyagi, Eric Beyne

10-1

Development of Multi-Stack Process on Wafer-on-Wafer (WOW)
Koji Fujimoto1,4, Nobuhide Maeda1, Hideki Kitada1, Youngsuk Kim1, Akihito Kawai2, Kazuhisa Arai2, Tomoji Nakamura3, Kousuke Suzuki4 and Takayuki Ohba1 / The University of Tokyo1, DISCO Corporation2, Fujitsu Laboratories Ltd.3, Dai Nippon Printing Co., Ltd.4

10-2

Room-temperature Si-Si and Si-SiN wafer bonding
Ryuichi Kondou1, Chenxi Wang1 and Tadatomo Suga1,2 / The University of Tokyo1, JST-CREST2

10-3

Thermal Stress Analysis of the 3D Die Stacks with Low-Volume Interconnections
Sayuri Kohara, Katsuyuki Sakuma, Yoshikazu Takahashi, Tohoyiro Aoki, Kuniaki Sueoka, Keiji Matsumoto, Paul S. Andry, Cornelia K. Tsang, Edmund J. Sprogis, John U. Knickerbocker and Yasumitsu Orii / IBM Japan, Ltd.

10-4

Wafer and/or chip bonding adhesives for 3D package
Toshihisa Nonaka, Koichi Fujimaru, Akira Shimada, Noboru Asahi, Yoshiko Tatsuta, Hiroyuki Niwa and Yasuko Tachibana / Toray Industries, Inc.


Author's Interview (20 min.)

Room 211
13:00 - 14:40 Session 11: Mechanical Design (MD-1)
Session Chair: Masazumi Amagai, Tadaaki Mimura

11-1

Review on the high temperature warpage measurement using shadow moire
Yong Goo Um and Jin Young Khim /Amkor Technology Korea

11-2

Warpage mechanism of single-sided molded package studied with viscoelastic analysis
Yusuke Komoto / NITTO DENKO Corporation

11-3

Vibration test durability on large BGA assemblies: Evaluation of reinforcement techniques
Matthieu Berthou1,2,3, Hua Lu4, Pascal Retailleau1, Helene Fremont2, Alexandrine Guedon-Gracia2, Catherine Jephos-Davennel3, Christopher Bailey4/MBDA France1, IMS Bordeaux Univ-Bordeaux12, DGA CELAR3, The University of Greenwich4

11-4

The Development of Cleaving - DBG + CMP process
Shinya Takyu, Mika Kiritani, Tetsuya Kurosawa and Noriko Shimizu / Toshiba Corporation Semiconductor Company


- Author's Interview (20 min.)
-

15:10 - 16:50 Session 12: Mechanical Design (MD-2)
Session Chair: Masazumi Amagai, Seok-Hwan HUH

12-1

Thermal stress analysis of FCBGA during cooling under reflow process
Chihiro J. Uchibori and Michael Lee / Fujitsu Labs, America, Inc.

12-2

Assembly-Stress-Mechanism in Pad Areas of Flip Chip Package on High-k/Metal gate Transistors
Yukitoshi Ota, Fumito Itoh, Kazuhiro Ishikawa, Kiyomi Hagihara, Takeshi Matsumoto, Teppei Iwase, Yutaka Itoh and Hiroshige Hirano / Panasonic Corporation


Author's Interview (20 min.)

August 26, 2010

Room 213: Session Chair: Hiroshi Yamada
9:30 - 10:15 Plenary Speech 7

3D Packaging Trends: From Stacked Die to 3D ICs with TSV
E. Jan Vardaman (President, TechSearch International, Inc.)
10:15 - 11:00 Plenary Speech 8
Advanced Electrical Measurement and Evaluation Technology for 3D LSI Chip Stacking Integration Technology,
Masahiro Aoyagi (Chair, CPMT Society Japan Chapter; the National Institute of Advanced Industrial Science and Technology)


Room 211

11:10 - 12:10 Session 13: Thermal Design (TD-1)
Session Chair: Atsushi Nakamura, Kishio Yokouchi

13-1

Heat spreader technology for silicon chip
Tomoyuki Kosakabe, Masataka Mochizuki, Koichi Mashiko, Yuji Saito, Fumitoshi Kiyooka, Yasuhiro Horiuchi, Gerald Cabusao and Thang Nguyen /Fujikura Ltd.

13-2

A Study of Thermal Performance for Chip-in-Substrate type LED Package Structure
Yen-Fu Su1, Tuan-Yu Hung1, Shin-Yueh Yang1 and Kuo-Ning Chiang2 / National Tsing Hua University1, National Center for High-Performance Computing2


- Author's Interview (10 min.)
-

13:20 - 15:20 Session 14: Thermal Design (TD-2)
Session Chair: Atsushi Nakamura, Kishio Yokouchi

14-1

Study on the Application of Thermal Interface Materials for Integration of HP-LEDs
Jun Wu1,2, Meilin Zhuang2, Shuzhi Li2, Weiqiao Yang2 and Jianhua Zhang1 / Shanghai University1, Shanghai Research Center of Solid-state Lighting Engineering and Technology2

14-2

Structure function based thermal resistance & thermal capacitance measurement for semiconductor packages
Yafei Luo / Mentor Graphics Japan Co., Ltd.

14-3

Data center energy conservation utilizing heat pipe based ice storage system
Gerald Cabusao, Masataka Mochizuki, Koichi Mashiko, Tetsuya Kobayashi, Randeep Singh, Thang Nguyen and Xiao Ping Wu / Fujikura Ltd.


- Author's Interview (20 min.)
-

Room 213
11:10 - 12:10 Session 15: Material (ML-1)
Session Chair: Itsuo Watanabe, William Chen

15-1

Invited : Recent Advance in Anisotropic Conductive Adhesives (ACAs) Materials and Processing Technology
Kyung-Wook Paik / Korea Advanced Institute of Science and Technology (KAIST)

15-2

Micro- Solder Precoat Technology by Precoat by Powder Sheet method
Kaichi Tsuruta, Takeo Kuramoto, Takeo Saitou and Manabu Muraoka / Senju Metal Industry Co.


- Author's Interview (10 min.)
-

13:20 - 15:20 Session 16: Material (ML-2)
Session Chair: Atsushi Okuno, Ricky Lee

16-1

Preparation of Active Layer of Solar Cells Device by F8T2 Blending with PCBM
Han-Sheng Huang , Po-Yi Lu , Cho-Liang Chung and Shen-Li Fu / I-Shou University

16-2

A novel polymer technology for underfill
Osamu Suzuki1, Toshiyuki Sato1, Pawel Czubarow2 Tomasz Waechol2 and Dave Son3/ NAMICS Corporation1, eM-TECH, LLC2, Southern Methodist University3

16-3

Transparent Encapsulating Resin for Automotive Applications
Hisataka Ito, Hiroshi Noro and Shinya Oota / NITTO DENKO Corporation

16-4

High reliability epoxy encapsulating compound for power module
Yuya Kitagawa, Satomi Yano, Hironori Kobayashi and Aya Mizushima / NITTO DENKO Corporation


- Author's Interview (20 min.)
-

15:30 - 17:30 Session 17: Material (ML-3)
Session Chair: Hiroshi Manita, Itsuo Watanabe

17-1

Phase Transformation of Metallic Nanoparticle Deposites for the Electrodes of Flexible Electronics
Tzu-Hsuan Kao2, Jenn-Ming Song1, Jian-Yih Wang1 and In-Gann Chen2 /National Dong Hwa University1, National Cheng Kung University2

17-2

A New, Cost-effective Coreless Substrate Technology
Bernd K. Appelt, Bruce Su, Alex S.F. Huang and Yi‐Shao Lai/ ASE Group Inc.

17-3

Build-up Electrical Insulation Material with Low-Dielectric Tangent, Low-CTE and Low-Surface Roughness
Isao Suzuki, Toshiaki Tanaka, Akihiro Uenishi, Takayuki Kobayashi and Junnosuke Murakami/ Sekisui Chemical Co., Ltd.

17-4

Electroless Ni/Pd/Au Plating for Semiconductor Package Substrates -Effect of Gold Plating Combinations on Gold Wire Bonding Reliability-
Yoshinori Ejiri1, Takehisa Sakurai1, Yoshinori, Arayama2, Yoshiaki Tsubomatsu1, Shuuichi Hatakeyama1, Shigeharu Arike1, Yukihisa Hiroyama1 and Kiyoshi Hasegawa1 / Hitachi Chemical Co.,Ltd.1, Hitachi Chemical Techno Service Co., Ltd.2


- Author's Interview (20 min.)
-

Room 212
11:10 - 12:10 Session 18: Optoelectronics (OE-2)
Session Chair: Shigeru Nakagawa, Shigenori Aoki

18-1

Invited : Multichannel optical modules with an SF optical connector interface
Hiromasa Tanobe1, Shuichiro Asakawa1, Masaru Kobayashi2 and Junya Kobayashi1 /NTT Corporation1, NTT Advanced Technology Corp.2

18-2

High-bandwidth optical MCM: FPGA with optical I/O on waveguide-integrated SLC
Masao Tokunari, Jean Benoit Heroux and Shigeru Nakagawa / IBM Japan, Ltd.


- Author's Interview (10 min.)
-

13:20 - 15:20 Session 19: Optoelectronics (OE-3)
Session Chair: Shigeru Nakagawa, Dausuke Iguchi

19-1

4-Ch × 10-Gb/s chip-to-chip optical interconnections with optoelectronic packages and optical waveguide separated from PCB
Yutaka Takagi, Atsushi Suzuki, Toshikazu Horio, Takeshi Ohno, Toshifumi Kojima, Toshikatsu Takada, Satoshi Iio, Kazushige Obayashi and Masahiko Okuyama / NGK Spark Plug CO., Ltd.

19-2

1060-nm 10-Gb/s x12-channel parallel-optical modules for optical interconnects
Toshinori Uemura, Yozo Ishikawa, Yoshinobu Nekado, Atsushi Izawa, Masakazu Yoshihara and Hideyuki Nasu / Furukawa Electric Co., Ltd.

19-3

High Throughput On-board Parallel Optical Modules Using Multi-chip Visual Alignment Technique
Kenichro Yashiki1, Takara Sugimoto2, Ichiro Ogura1 and Kazuhiro Kurata1 / NEC Corporation1, NEC Yamanashi Ltd.2

19-4

Relationship between alignment errors of optical components and power consumption in optoelectronic devices
Hironobu Morita and Minoru Watanabe / Shizuoka University


- Author's Interview (20 min.)
-

15:30 - 17:05 Session 20: Optoelectronics (OE-4)
Session Chair: Shigenori Aoki, Dausuke Iguchi

20-1

Polymeric multi/demultiplexers using light-induced self-written waveguides for cost-effective optical interconnection
Tatsuya Yamashita1, Akari Kawasaki1, Manabu Kagami1, Takashi Yasuda2 and Hideki Goto2 / Toyota Central R&D Labs., Inc.1, TOYOTA Motor Corporation2

20-2

Soft-Lithographic Fabrication of Polymer Parallel Optical Waveguides with Graded-Index Cores for Board-Level Optical Interconnections
Takaaki Ishigure, Yosuke Nitta and Yusuke Sugimori / Keio University

20-3

Optical Waveguide Materials with High Thermal Reliability and Their Applications for High-density Optical Interconnections
Tomoaki Shibata1, Tatsuya Makino1, Atsushi Takahashi1, Yasunobu Matsuoka2 and Tosahiki Sugawara2 / Hitachi Chemical Co.,Ltd.1, Hitachi Ltd.2


- Author's Interview (20 min.) -

Last updated:  2010/ 9/13