IEEE CPMT Symposium Japan,
formerly VLSI Package Workshop in Japan
Aug.24 - 26, 2010

The University of Tokyo, Hongo Campus
Faculty of Engineering Bldg.2
Sanjo Conference Hall

Thanks for many participants
See you next symposium.

You can show the highlight of symposium.

< Best Paper >
"Polymeric Multi/Demultiplexers using light-induced self-written waveguides for cost-effective optical interconnection"
Tatsuya Yamashita (Toyota Central R&D Labs)

"A wafer-level system integration technology for flexible pseudo-SOC incorporates MEMS-CMOS heterogeneous devices"
Hiroshi Yamada (Toshiba)

< Young Award >
"Guard-Ring Effect for Through Silicon Via (TSV) Coupling Reduction",
Jonghyun Cho (KAIST)

"Room-temperature Si-Si and Si-SiN wafer bonding"
Ryuichi Kondou (University of Tokyo)

"Assembly-Stress-Mechanism in Pad Areas of Flip Chip Package on High-k/Metal gate Transistors",
Yukitoshi Ota (Panasonic)

Technical Topics of this Workshop